1. Field of the Invention
The invention relates to example methods of fabricating semiconductor devices and, more particularly, to example methods of forming small via structures on a semiconductor device during the process of fabricating a phase change memory device.
2. Description of the Related Art
Non-volatile memory devices share an ability to maintain stored data for a period of time even when the power supply to the memory device is interrupted. Accordingly, non-volatile memory devices are widely utilized computers, mobile communication systems, memory cards, and other applications in which the memory may be powered and accessed infrequently.
Flash memory devices are a class of non-volatile memory devices that typically employ memory cells having a stacked gate structure. The stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode which are sequentially stacked on a channel region. The reliability and program efficiency of the flash memory cells can be enhanced by improving the film quality of the tunnel oxide layer and increasing the coupling ratio of the memory cell.
Phase change memory devices are another class of non-volatile memory devices that operate in a different manner than flash memory devices. The basic construction and operation of a phase change memory device utilizes an electrically erasable and programmable phase change material.
A unit memory cell in a typical phase change memory device includes an access device and a data storage element that is connected in series with the access device. The data storage element typically includes a bottom electrode electrically connected to the access device, and a phase change material layer in contact with the bottom electrode. When a write current flows through the access device and the bottom electrode, Joule heat (sometimes referred to as I2R heat) is generated at an interface between the phase change material layer and the bottom electrode. The Joule heat tends to transform the phase change material layer into a more amorphous state or a more crystalline state.
As will be appreciated, this phase change does not need to be a conversion between a completely crystalline state and completely amorphous state, but rather only conversion between two detectable and distinguishable states having a local order within two separate regions falling within the composition spectrum between a completely crystalline state and a completely amorphous state. The phase change material layer will also exhibit a range of electrical characteristics or parameters depending on its structural state as reflected in, for example, an increasing resistance value associated with an increasingly the amorphous state and a decreasing resistance value associated with an increasingly crystalline state.
One drawback associated with phase change memory devices is the relatively high write current values that are required in order to induce a detectable phase change in the phase change material. The need to apply the necessary high write current level tends to limit the degree to which the size, and associated current carrying capacity, of an associated access device and address line used for delivering the write current to each cell can be reduced. The sizing of the access device and address lines will, consequently, tend to determine the degree of integration that can be achieved in a phase change memory device.
One approach for reducing the write current requirements has been directed to utilization of a confined structure in which the phase change material layer is formed in a fine via hole that exposes a region of a bottom electrode for reducing the contact area with the bottom electrode. The phase change memory device having the confined structure provides a reduced volume of material within which the phase change will be induced, thereby increasing the effective current density of the write current through the phase change material. Examples of phase change memory devices incorporating a confined structure are disclosed in U.S. Pat. No. 6,117,720 and U.S. patent publication no. 2003-73295, the contents of which are incorporated herein, in their entirety, by reference and for all purposes to the extent consistent with the disclosure provided below.
In the meantime, in order to enhance the degree of integration in the phase change memory device having the confined structure, the diameter of the via hole that will be filled with the phase change material layer should be decreased. For example, in order to fabricate a highly integrated phase change memory device of 256-megabyte class, the via hole should be formed to have a diameter of about 50 nm or less. Typically, however, the phase change material layer is deposited using a sputtering method that tends to exhibit relatively poor step coverage that tends to complicate with efforts to uniformly fill fine via holes with the phase change material layer.
In particular, during conventional sputtering deposition, an overhanging region of material tends to form around the upper edge or lip of the via hole as the phase change material layer is being deposited. This overhanging region increases the likelihood that defects such as voids may be created within the phase change material layer filling the via hole. The likelihood of such defects also tends to increase as the aspect ratio of the via hole increases, e.g., where the diameter of the via hole is decreased while the via hole depth remains relatively unchanged.
In addition, as described in U.S. Pat. No. 6,117,720, a chemical mechanical polishing (CMP) process may be utilized to define the phase change material layer within the via hole. However, if the phase change material, for example an alloy containing germanium-antimony (sometimes referred to as stibium)-tellurium (GST), is volatile or otherwise overly susceptible to the CMP process, excessive amounts of the material can be removed during the CMP process. One approach for addressing this issue is outlined in U.S. patent publication no. 2003-73295, in which the loss of the phase change material layer during the CMP process may be reduced by forming the top electrode layer on the GST alloy layer filling the via hole and then anisotropically etching the conductive (electrode) layer and the phase change material layer to form a stacked structure.
During such an anisotropic etch process, however, the exposed side portions of the GST alloy layer may suffer varying degrees of etch damage. In particular, as the size of the GST alloy layer pattern is decreased to improve the degree of integration of the phase change memory device, the GST alloy layer pattern tends to become more susceptible to etch damage, thereby increasing the likelihood that the operating characteristics of the phase change memory device may be degraded and reduce the process yield and/or reliability of the resulting memory devices.